The present invention relates to a method for manufacturing a custom-circuit LSI, and a gate array device used as the base component of a custom-circuit LSI.
More and more gate array devices are used as LSIs of various types come into use in various apparatus. These gate arrays are, so to speak, semi-custom LSI devices. Their logic architectures are determined by lay-out masks used at the final stage of manufacture. A gate array device comprises a semiconductor chip and a number of logic cells (e.g., 2-input NAND gates, 2-input NOR gates) arranged in matrix on the chip. The logic cells are to be interconnected so as to perform a custom-circuit logic function. The user-designer first designs a custom-circuit LSI to be made in the form of an IC, then selects one of the commercially available gate array chips, which has the number of logic cells corresponding to the scale of the custom-circuit, and finally designs a metal pattern for interconnecting these logic cells, in accordance with the logic architecture of the custom-circuit. To simulate the interconnection of the logic cells, the user-designer uses a computer aided design (CAD) system. This system helps him design the metal pattern within a short time.
If a large-scale custom-cicuit LSI is manufactured, the apparatus with this LSI will be more reliable, smaller and less expensive than otherwise. It is therefore desired at present that an gate array device have a higher packing density.
Some problems arise when a gate array having about 6000 or more logic cells is used. As mentioned above, a CAD system is indispensable in shortening the time necessary for designing custom-circuit LSIs. The existing CAD system, however, can by itself design a practical metal pattern which can interconnect about 2000 logic cells or less. To design a metal pattern for interconnecting 6000 cells or more, the human designer has to repeat the designing procedure many times. After all, many hours will be inevitably spent to provide a metal pattern which connects 6000 or more logic cells.
Indeed the user-designer can develop custom-circuit LSIs of different functions if he uses such gate arrays as base components. However, he cannot design a large-scale logic circuit without making a considerable mistake. Further, the number of gates incorporated in the custom-circuit LSI he designed may not be equal to the number of logic cells which must be build in the gate array of the LSI, depending on the fashion in which the neighboring logic cells are interconnected. That is, some of the logic cells of the array cannot be connected directly to each other, and extra logic cells must be provided to connect these specific logic cells. The larger scale the custom-circuit LSI has, the more difficult it will be for the user-designer to determine how many logic cells should be included in the gate array. As a result, it is hard for him to select a proper gate array and not to leave many logic cells useless.